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| ccm-pfc ICE2PCS05 ICE2PCS05g standalone power factor correction (pfc) controller in continuous conduction mode (ccm) never stop thinking. version 1.0, 09 oct 2008 power management & supply
edition 2008-10-09 published by infineon technologies ag 81726 mnchen, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical valu es stated herein and/or any information regarding the application of the device, infineon technologies her eby disclaims any and all warranties and liabilities of any kind, including wi thout limitation, warranties of non-infrin gement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may be used in life-s upport devices or systems onl y with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representat ives worldwide: see our webpage at http:// www.infineon.com coolmost?, coolset? are trademarks of infineon technologies ag. ccm-pfc revision history: datasheet previous version: page subject s ( major changes since last revision) ccm-pfc ICE2PCS05 ICE2PCS05g version 1.0 3 09 oct 2008 type package ICE2PCS05 pg-dip-8 ICE2PCS05g pg-dso-8 standalone power factor correction (pfc) controller in continuous conduction mode (ccm) ICE2PCS05 pg-dip-8 test ICE2PCS05g pg-dso-8 product highlights ? leadfree dip and dso package ? wide input range ? optimized for applications which require fast startup ? output power controllable by external sense resistor ? programmable operating frequency ? output over-voltage protection ? fast output dynamic response during load jumps features ? ease of use with few external components ? supports wide range ? average current control ? external current and voltage loop compensation for greater user flexibility ? programmable operating/switching frequency (20khz - 250khz) ? max duty cycle of 95% (at 25c) at 125khz ? trimmed internal reference voltage (3v+ 2% at 25c) ? vcc under-voltage lockout ? cycle by cycle peak current limiting ? output over-voltage protection ? open loop detection ? enhanced dynamic response ? short startup(softstart) duration ? fulfills class d requ irements of iec 1000-3-2 ? soft overcurrent protection ? description the ICE2PCS05/g is a 8-pin wide input range controller ic for active power factor correction converters. it is de- signed for converters in boost topology, and requires few external components. its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the ic. the ic operates in the ccm with average current control, and in dcm only under light load condition. the switching frequency is programmable by the resistor at pin 4. both compensations for the current and voltage loop are exter- nal to allow full user control. there are various protection features incorporated to en- sure safe system operation conditions. the internal refer- ence is trimmed (3v+ 2%) to ensure precise protection and control level. the device has a fast startup time with con- trolled peak start up current. 85 ... 265 vac emi-filter voltage loop compensation protection unit variable oscillator current loop compensation pwm logic driver ICE2PCS05/ ICE2PCS05g pfc-controller vcc auxiliary supply v out typical application switch ramp generator freq icomp vsense vcomp isense gnd nonlinear gain gate ccm-pfc ICE2PCS05/g version 1.0 4 09 oct 2008 1 pin configurati on and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 representative block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 system protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.1 soft over current control (s oc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.2 peak current limit (pcl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.3 open loop protection / input under vo ltage protect (olp) . . . . . . . . . . . 9 3.4.4 over-voltage protection (ovp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 average current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.1 complete current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.2 current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.3 pulse width modulation (pw m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.4 nonlinear gain block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 pwm logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8.1 voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8.2 enhanced dynamic response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 output gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 absolute maximum rating s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.2 variable frequency section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.4 system protection section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.5 current loop section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.6 voltage loop section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.7 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 version 1.0 5 09 oct 2008 ccm-pfc ICE2PCS05/g pin configurati on and functionality 1 pin configuration and functionality 1.1 pin configuration figure 1 pin configuration (top view) 1.2 pin functionality gnd (ground) the ground potential of the ic. icomp (current loop compensation) low pass filter and compensation of the current control loop. the capacitor which is connected at this pin integrates the output curren t of ota2 and averages the current sense signal. isense (current sense input) the isense pin senses the voltage drop at the external sense resistor (r1). this is the input signal for the average current regulation in the current loop. it is also fed to the peak cu rrent limitation block. during power up time, high inrush currents cause high negative voltage drop at r1, driving currents out of pin 3 which could be beyond the absolute maximum ratings. therefore a series resistor (r2) of around 220 ? is recommended in order to limit this current into the ic. freq (frequency setting) this pin allows the setting of the operating switching frequency by connecting a resistor to ground. the frequency range is from 20khz to 250khz. vsense (voltage sense/feedback) the output bus voltage is sensed at this pin via a resistive divider. the reference voltage for this pin is 3v. vcomp (voltage loop compensation) this pin provides the compensation of the output voltage loop with a compensation network to ground (see figure 2). this also gives the soft start function which controls an increasing ac input current during start-up. vcc (power supply) the vcc pin is the positive supply of the ic and should be connected to an external auxiliary supply. the operating range is between 11v and 26v. the turn-on threshold is at 11.8v and under voltage occurs at 11v. there is no internal clamp for a limitation of the power supply. gate the gate pin is the output of the internal driver stage, which has a capability of 1.5a instantaneous source and 2.0a instantaneous sink current. its gate drive voltage is clamped at 15v (typically). pin symbol function 1 gnd ic ground 2 icomp current loop compensation 3 isense current sense input 4 freq switching frequency setting 5 vcomp voltage loop compensation 6 vsense v out sense (feedback) input 7 vcc ic supply voltage 8 gate gate drive output package pg-dip-8 / pg-dso-8 1 6 7 8 4 3 2 5 gate gnd icomp isense vcc vsense freq vcomp ccm-pfc ICE2PCS05/g representative block diagram version 1.0 6 09 oct 2008 2 representative block diagram figure 2 representative block diagram ICE2PCS05/g 85 ... 265 vac vout auxiliary supply c2 1.5v -1.43x ota3 1.7v isense gate vsense vcc freq c1 vcomp ota2 icomp 4.2v powerdown uvlo vcc 0.6v gnd pwm comparator ramp generator variable oscillator toff min over-current comparator deglitcher pwm logic gate driver undervoltage lockout open-loop protect voltage loop current loop compensation protection block 3.25v overvoltage protect peak current limit current loop nonlinear gain c3 c4 ota1 3v +/-30a, 39s 1.0ms +/-50a linear range r1 r5 l1 c2 r3 r4 c3 c5 c4 r6 r2 s2 vin d1 fault 2.85v 3.18v 0.75 v 0 -ve window detect +ve 0 -ve soft over current control s1 fault op1 current sense opamp osc clk 2.5%t r s r s protection logic c1 rfi filter d2 ... d5 r7 d6 300ns ccm-pfc ICE2PCS05/g functional description version 1.0 7 09 oct 2008 3.1 general the ICE2PCS05/g is a 8 pin control ic for power factor correction converters. it comes in both dip and dso packages and is suitable for wide range line input applications from 85 to 265 vac. the ic supports converters in boost topology and it operates in continuous conduction mode (ccm) with average current control. the ic operates with a cascaded control; the inner current loop and the outer voltage loop. the inner current loop of the ic contro ls the sinusoidal profile for the average input current. it uses the dependency of the pwm duty cycle on the line input voltage to determine the corresponding input current. this means the average input current fo llows the input voltage as long as the device operates in ccm. under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (dcm). in dcm, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the class d requirement of iec 1000- 3-2. the outer voltage loop controls the output bus voltage. depending on the load condition, ota1 establishes an appropriate voltage at vcomp pin which controls the amplitude of the average input current. the ic is equipped with various protection features to ensure safe operating condition for both the system and device. important protec tion features are namely open-loop protection, curren t limitation and output over-voltage protection. 3.2 power supply an internal under voltage lockout (uvlo) block monitors the vcc power supply. as soon as it exceeds 11.8v and the voltage at pin 6 (vsense) is >0.6v, the ic begins operating its gate drive and performs its startup as shown in figure 3. . figure 3 state of operation respect to vcc if vcc drops below 11v, the ic is off. the ic will then be consuming typically 300 a, whereas consuming 13ma during normal operation. the ic can be turned off and forced into standby mode by pulling down the voltage at pin 6 (vsense) to lower than 0.6v. the current consumption is reduced to 300a in this mode. 3.3 start-up figure 4 shows the operation of voltage loop?s ota1 during startup. the vcomp pin is pull internally to ground via switch s1 during uvlo and other fault conditions (see later section on ?system protection?). during power up when v out is less than 83% of the rated level, ota1 sources an output current, maximum 30 a, into the compensation network at pin 5 (vcomp) causing the voltage at this pin to rise linearly. this results in a controlled linear increase of the input current from 0a thus reducing the stress on the external component. figure 4 startup circuit as v out has not reached within 5% from the rated value, vcomp voltage is level-shifted by the window detect block as shown in figure 5, to ensure there is fast boost up of the output voltage. when v out approaches its rated value, ota1?s sourcing current drops and t he level shift of the window detect block is removed. the normal voltage loop then takes control. v cc ( v vsense > 0.6 v) 11.8 v 11.0 v t off start up open loop/ standby normal operation ic's state off normal operation ( v vsense < 0.6 v) ( v vsense > 0.6 v) vcomp c5 c4 vsense ota1 3v ICE2PCS05/g protect r3 + r4 r4 x v out ) ( r6 s1 3 functional description ccm-pfc ICE2PCS05/g functional description version 1.0 8 09 oct 2008 figure 5 startup with cont rolled maximum current 3.4 system protection the ic provides several prot ection features in order to ensure the pfc system in safe operating range. depending on the input line voltage (v in ) and output bus voltage (v out ), figure 7 and 8 show the conditions when these protections are active. figure 6 v in related protection features figure 7 v out related protection features the following sections describe the functionality of these protection features. 3.4.1 soft over current control (soc) the ic is designed not to support any output power that corresponds to a voltage lower than -0.75v at the isense pin. a further increa se in the inductor current, which results in a lower i sense voltage, will activate the soft over current cont rol (soc). this is a soft control as it does not directly switch off the gate drive. it acts on the nonlinear gain block to result in a reduced pwm duty cycle. av(i in ) v out t v out =rated 95%rated window detect normal control t max vcomp current 83%rated vcomp level-shifted vcomp t v in (vac) vcc > v ccuvlo normal operation ic off vcc ccm-pfc ICE2PCS05/g functional description version 1.0 10 09 oct 2008 3.6 average current control 3.6.1 complete current loop the complete system current loop is shown in figure 11. figure 11 complete system current loop it consists of the current loop block which averages the voltage at pin isense, resulted from the inductor current flowing across r1. the averaged waveform is compared with an internal ramp in the ramp generator and pwm block. once the ramp crosses the average waveform, the comparator c1 turns on the driver stage through the pwm logic block. the nonlinear gain block defines the amplitude of the inductor current. the following sections describe the functionality of each individual blocks. 3.6.2 current loop compensation the compensation of the current loop is done at the icomp pin. this is the ota2 output and a capacitor c3 has to be installed at this node to ground (see figure 11). under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. this pin is internally shorted to 4.2v in the event of ic shuts down when olp and uvlo occur. 3.6.3 pulse width modulation (pwm) the ic employs an average current control scheme in continuous conduction mode (ccm) to achieve the power factor correction. assuming the voltage loop is working and output voltage is kept constant, the off duty cycle d off for a ccm pfc system is given as from the above equation, d off is proportional to v in . the objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle d off , and thus to the input voltage v in . figure 12 shows the scheme to achieve the objective. figure 12 average current control in ccm the pwm is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (icomp). the pwm cycle starts with the gate turn off for a duration of t offmin (250ns typ.) and the ramp is kept discharged. the ramp is then allowed to rise after t offmin expires. the off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. this results in the proportional relationship between the average current and the off duty cycle d off . figure 13 shows the timing diagrams of t offmin and the pwm waveforms. figure 13 ramp and pwm waveforms 3.6.4 nonlinear gain block the nonlinear gain block controls the amplitude of the regulated inductor current. the input of this block is the r s ICE2PCS05/g vout l1 c2 r3 r4 gate driver d1 from full-wave retifier gate r1 r2 ota2 icomp 4.2v current loop compensation current loop nonlinear gain 1.0ms +/-50ua (linear range) c3 s2 fault isense c1 pwm comparator pwm logic q input from voltage loop voltage proportional to averaged inductor current r7 d off v in v out ------------- - = t ave(i in ) at icomp ramp profile gate drive t offmin 2.5% of t v cref (1) v ramp pwm ramp released pwm cycle (1) v cref is a function of v icomp t ccm-pfc ICE2PCS05/g functional description version 1.0 11 09 oct 2008 voltage at pin vcomp. this block has been designed to support the wide input voltage range (85-265vac). 3.7 pwm logic the pwm logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. the speed of the logic gates in this block, together with the width of the reset pulse t offmin , are designed to meet a maximum duty cycle d max of 95% at the gate output under 136khz of operation. in case of high input currents which result in peak current limitation, the gate will be turned off immediately and maintained in off state for the current pwm cycle. the signal toffmin resets (highest priority, overriding other input signals) both the current limit latch and the pwm on latch as illustrated in figure 14. figure 14 pwm logic 3.8 voltage loop the voltage loop is the outer loop of the cascaded control scheme which controls the pfc output bus voltage v out . this loop is closed by the feedback sensing voltage at vsense which is a resistive divider tapping from v out . the pin vsense is the input of ota1 which has an internal reference of 3v. figure 15 shows the important blocks of this voltage loop. 3.8.1 voltage loop compensation the compensation of the voltage loop is installed at the vcomp pin (see figure 15). this is the output of ota1 and the compensation must be connected at this pin to ground. the compensation is also responsible for the soft start function which c ontrols an increasing ac input current during start-up. figure 15 voltage loop 3.8.2 enhanced dynamic response due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. this may cause additional stress to the bus capacitor and the switching transistor of the pfc in the event of heavy load changes. the ic provides therefore a ?window detector? for the feedback voltage v vsense at pin 6 (vsense). whenever v vsense exceeds the reference value (3v) by + 5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. this change in duty cycle is bypassing the slow changing vcomp voltage, thus results in a fast dynamic response of v out . 3.9 output gate driver the output gate driver is a fa st totem pole gate drive. it has an in-built cross conduction currents protection and a zener diode z1 (see figure 16) to protect the external transistor switch against undesirable over voltages. the maximum voltage at pin 8 (gate) is typically clamped at 15v. the output is active high and at vcc voltages below the under voltage lockout threshold v ccuvlo , the gate drive is internally pull low to maintain the off state. g1 r s l1 r s l2 peak current limit current loop pwm on signal toffmin 2.5% of t current limit latch pwm on latch high = turn gate on q q vcomp vsense c5 c4 r6 ota1 3v v in av(i in ) nonlinear gain t vout l1 c2 r3 r4 gate driver current loop + pwm generation d1 from full-wave retifier gate r7 ccm-pfc ICE2PCS05/g functional description version 1.0 12 09 oct 2008 figure 16 gate driver gate external mos z1 vcc gate driver pwm logic high to turn on lv * lv: level shift ICE2PCS05/g ccm-pfc ICE2PCS05/g electrical characteristics version 1.0 13 09 oct 2008 4 electrical characteristics 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings , which when being exceeded may lead to destruction of the integrated circuit. 4.2 operating range note: within the operati ng range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. v cc supply voltage v cc -0.3 25 v freq voltage v freq -0.3 5 v icomp voltage v icomp -0.3 5 v isense voltage v isense -20 5 v 2) isense current i isense -1 1 ma recommended r2=220 ? vsense voltage v vsense -0.3 5 v vsense current i vsense -1 1 ma r3>400k ? vcomp voltage v vcomp -0.3 5 v gate voltage v gate -0.3 17 v clamped at 15v if driven internally. junction temperature t j -40 150 c storage temperature t s -55 150 c thermal resistance junction-ambient for dso-8-13 r thja (dso) - 185 k/w pg-dso-8-13 thermal resistance junction-ambient for dip-8-4 r thja (dip) - 90 k/w pg-dip-8-4 esd protection v esd - 2 kv human body model 1) 1) according to eia/jesd22-a114-b (dischar ging a 100pf capacitor through a 1.5k ? series resistor) 2) absolute isense current should not be exceeded parameter symbol limit values unit remarks min. max. v cc supply voltage v cc v ccuvlo 25 v junction temperature t jcon -40 125 c ccm-pfc ICE2PCS05/g electrical characteristics version 1.0 14 09 oct 2008 4.3 characteristics note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 40 c to 125 c.typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc =18v is assumed for test condition . 4.3.1 supply section 4.3.2 variable frequency section parameter symbol limit values unit test condition min. typ. max. vcc turn-on threshold v ccon 11.4 11.8 12.7 v vcc turn-off threshold/ under voltage lock out v ccuvlo 10.4 11.0 11.7 v vcc turn-on/off hysteresis v cchy 0.65 0.8 1.4 v start up current before v ccon i ccstart - 450 1100 av vcc =v vccon -0.1v operating current with active gate i cchg -1520mar5 = 33k ? c l = 4.7nf operating current during standby i ccstdby - 700 1300 av vsense = 0.5v v icomp = 4v parameter symbol limit values unit test condition min. typ. max. switching frequency (typical) f swnom 124 136 147 khz r5 = 33k ? switching frequency (min.) f swmin 17 21 25 khz i freq =v freq / 234k ? switching frequency (max.) f swmax 250 285 315 khz r5 = 15k ? voltage at freq pin v freq 1.65 1.70 1.76 v ccm-pfc ICE2PCS05/g electrical characteristics version 1.0 15 09 oct 2008 4.3.3 pwm section 4.3.4 system protection section parameter symbol limit values unit test condition min. typ. max. max. duty cycle d max 92 95 98.5 % f sw = f swnom (r5 = 33k ? ) min. duty cycle d min 0%v vcomp = 0v, v vsense = 3v v icomp = 4.3v min. off time t offmin 100 250 580 ns v vsense = 3v v isense = 0.1v (r5 = 33k ? ) parameter symbol limit values unit test condition min. typ. max. open loop protection (olp) vsense threshold v olp 0.55 0.6 0.65 v peak current limitation (pcl) isense threshold v pcl -1.16 -1.04 -0.95 v soft over current control (soc) isense threshold v soc -0.75 -0.68 -0.61 v output over-voltage protection (ovp) v ovp 3.13.253.4 v the parameter is not subject to production test - verified by design/characterization ccm-pfc ICE2PCS05/g electrical characteristics version 1.0 16 09 oct 2008 4.3.5 current loop section 4.3.6 voltage loop section parameter symbol limit values unit test condition min. typ. max. ota2 transconductance gain gm ota2 0.8 1.0 1.3 ms at temp = 25c ota2 output linear range 1) i ota2 - 50- a icomp voltage during olp v icompf 3.9 4.2 - v v vsense = 0.5v parameter symbol limit values unit test condition min. typ. max. ota1 reference voltage v ota1 2.92 3.00 3.08 v measured at vsense ota1 transconductance gain gm ota1 26 39 51 s ota1 max. source current under normal operation i ota1so 18 30 38 av vsense = 2v v vcomp = 3v ota1 max. sink current under normal operation i ota1sk 21 30 41 av vsense = 4v v vcomp = 3v enhanced dynamic response vsense high threshold vsense low threshold v hi v lo 3.09 2.76 3.18 2.85 3.26 2.94 v v vsense input bias current at 3v i vsen3v 0-1.5 av vsense = 3v vsense input bias current at 1v i vsen1v 0-1 av vsense = 1v vcomp voltage during olp v vcompf 00.20.4vv vsense = 0.5v i vcomp = 0.5ma ccm-pfc ICE2PCS05/g electrical characteristics version 1.0 17 09 oct 2008 4.3.7 driver section parameter symbol limit values unit test condition min. typ. max. gate low voltage v gatel --1.2vv cc = 10v i gate = 5 ma -1.5vv cc = 10v i gate =20 ma -0.4-vi gate = 0 a --1.0vi gate = 20 ma -0.2 0 - v i gate = -20 ma gate high voltage v gateh - 14.8 - v v cc = 25v c l = 4.7nf - 14.8 - v v cc = 19v c l = 4.7nf 7.8 9.2 - v v cc = v vccoff + 0.2v c l = 4.7nf gate rise time t r -60-nsv gate = 2v ...12v c l = 4.7nf gate fall time t f -50-nsv gate = 12v ...2v c l = 4.7nf gate current, peak, rising edge i gate -1.5 - - a c l = 4.7nf 1) 1) design characteristics (not meant for production testing) gate current, peak, falling edge i gate --2.0ac l = 4.7nf 1) ccm-pfc ICE2PCS05/g outline dimension version 1.0 18 09 oct 2008 5 outline dimension figure 17 pg-dso-8 and pg-d ip-8 outline dimension ccm-pfc ICE2PCS05/g outline dimension version 1.0 19 09 oct 2008 ccm-pfc ICE2PCS05/g outline dimension version 1.0 20 09 oct 2008 ccm-pfc ICE2PCS05/g outline dimension version 1.0 21 09 oct 2008 qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineo n technologies ag |
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